Email :rathinamalav@iisc.ac.in

EDUCATION:

M.TECH (Electronics) Sir M.Visvesvaraya Institute of Technology, Bangalore, VTU, Karnataka
B.E (ECE) Government College of Engineering, Tirunelveli, Tamilnadu

RESEARCH INTERESTS:

I am interested in the design and development of testbeds to evaluate performance in a heterogeneous network under QOS constraints. I am currently exploring the use of these testbeds in Device to Device communication.

PROJECTS UNDERTAKEN:

• Implementation of jammers in SDR and performance evaluation of IEEE 802.3 devices in the presence of jammers.
• Testbed for cognitive Radio.
• Link capacity adjacent scheme (LCAS) protocol implementation in Stratix II FPGA using Altera Quartus II 8.0
• Algorithms for PAPR reduction.

PUBLICATIONS:

Rathinamala Vijay, Harsh pal Singh, Prabhakar T.V, Vinod Hegde, Pavan Shigehalli, “Air Cargo Monitoring: A Robust Tamper Detection and Reliable Communication System” IEEE Symposium on Industrial Embedded Systems (SIES 2018).